1. Field of the Invention
The present invention generally relates to semiconductor processing technologies and, more specifically, to a method for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer in semiconductor processing.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g. sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, metal interconnects with low resistance (e.g., copper and aluminum) provide conductive paths between the components on integrated circuits.
Typically, the metal interconnects are electrically isolated from each other by a dielectric bulk insulating material. When the distance between adjacent metal interconnects and/or the thickness of the dielectric bulk insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit.
In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 4.0) are needed. Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO2), silicate glass, fluorosilicate glass (FSG), and carbon doped silicon oxide (SiOC), among others.
In addition, a dielectric barrier layer often separates the metal interconnects from the dielectric bulk insulating materials. The dielectric barrier layer minimizes the diffusion of the metal into the dielectric bulk insulating material. Diffusion of the metal into the dielectric bulk insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit, or render it inoperative. The dielectric layer needs to have a low dielectric constant in order to maintain the low-k characteristic of the dielectric stack between conductive lines. The dielectric barrier layer also acts as an etch-stop layer for a dielectric bulk insulating layer etching process, so that the underlying metal will not be exposed to the etching environment. The dielectric barrier layer has a dielectric constant of about 5.5 or less. Examples of dielectric barrier layer are silicon carbide (SiC) and nitrogen containing silicon carbide (SiCN), among others.
Some integrated circuit components include multilevel interconnect structures (e.g., dual damascene structures). Multilevel interconnect structures can have two or more bulk insulating layers, low dielectric barrier layers, and metal layers stacked on top of one another. As an exemplary dual damascene structure shown in FIG. 1A, a dielectric bulk insulating layer 108 with an underlying dielectric barrier layer 106 are stacked on another previously formed interconnect with a conductive layer 104 embedded in another dielectric bulk insulating layer 102. As a via/trench etching process is completed and a via/trench 110 is defined on the dielectric bulk insulating layer 108, the exposed dielectric barrier layer 106 defined by the via/trench 110 is subsequently removed to expose the underlying conductive layer 104 so that the following deposited conductive layer 116 can be connected and jointed therethrough, as shown in FIG. 1B. However, the similarity of the selected materials of the bulk insulating layer 108 and dielectric barrier layer 106 results in similar etch properties therebetween, thereby causing poor selectivity during etching. As shown in FIG. 1C, as the dielectric barrier layer 106 is etched, the dielectric bulk insulating layer 108 may be attacked simultaneously by the reactive etchant species, resulting in non-uniformity or tapered profile on the top and/or sidewall of the layer 114. In embodiments where the underlying conductive layer 104 is not aligned with the trench opening 110, as shown in FIG. 1D, the underlying dielectric bulk insulating layer 102 may be attacked 112 during etching of the dielectric barrier layer 106 due to poor selectivity to the dielectric bulk insulating layer 102.
Therefore, there is a need for a method of etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer.